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      • 03. DISSERTATIONS AND THESIS
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      •   UMY Repository
      • 03. DISSERTATIONS AND THESIS
      • Students
      • Undergraduate Thesis
      • Faculty of Engineering
      • Department of Electrical Engineering
      • View Item
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      ANALISIS KUALITAS DAYA LISTRIK PADA GEDUNG ADMISI UNIVERSITAS MUHAMMADIYAH YOGYAKARTA

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      HALAMAN JUDUL (304.8Kb)
      HALAMAN PENGESAHAN (824.2Kb)
      ABSTRAK (127.4Kb)
      BAB I (177.6Kb)
      BAB II (571.6Kb)
      BAB III (193.8Kb)
      BAB IV (3.420Mb)
      BAB V (84.06Kb)
      DAFTAR PUSTAKA (72.65Kb)
      LAMPIRAN (377.0Kb)
      NASKAH PUBLIKASI (1.969Mb)
      Date
      2018-12-20
      Author
      FAISAL, RISKY MUHAMMAD
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      Abstract
      The power quality of the power system is one of the problems discussed in the research and dissertation of students, especially electrical engineering students. This problem is considered important, so that not a few engineers devote their attention in writing books that discuss in full about harmonics and losses of electrical voltage. Because of the attention to these problems, the Institute of Electrical and Electronic Engineers (IEEE) or other standardization institutions make boundaries that become international references in the matter of the influence of power quality. From the results of observations and measurements that have been made to the voltage values in the electricity distribution network in The Admission Building on Phase R is not in the ANSI / IEEE Power Quality standard because the highest value of Phase RST 227.8 V, 231.3 V and 227.1 V this value exceeds the tolerance value of + 5%. The results of observations and measurements that have been made on the value of voltage harmonics on the electricity distribution network in the Admissions Building at the RST phase are not in the ANSI / IEEE Power Quality standard because the highest values of Phase RST 6.40%, 6.40% and 6.10% V exceed the tolerance value limit. The results of observations and measurements of electricity in the UMY Admission Building, the authors get conclusions from the values that exceed the ANSI / IEEE standard in the SDP panel in the UMY Admission Building. From the measurement results in the Admission panel on December 5, 2018 to December 6, 2018 there are voltage irregularities between the RST phases where at 3:00 the voltage value is greater than the voltage value in working hours. This can be observed in the table where the peak voltage exceeds the ANSI / IEEE standard, at 3:00 a.m. also the power factor value decreases by 0,977 (06:20) which causes a loss of power and trigger the occurrence of excessive peak voltage that occurs unbalanced V and unbalanced I.
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      http://repository.umy.ac.id/handle/123456789/23741
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      • Department of Electrical Engineering

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